Verified yesterday
Sr Principal Product Validation Engineer
About the role
Cadence seeks Sr Principal Product Validation Engineer to lead functional verification of complex digital systems. Must be Electrical/Electronics/Computer Science Engineer with strong HDL (Verilog/VHDL) knowledge, experience in simulation/emulation, EDA tools debugging, SystemVerilog, C++, UVM, functional verification of SoC, protocols PCIe, USB3/4, DP. Process automation scripting required.
What you’ll bring
- Electrical/Electronics/CS Engineer
- Strong HDL (Verilog/VHDL) knowledge
- Simulation/emulation experience
- EDA tools debugging expertise
- SystemVerilog, C++, UVM proficiency
- Functional verification of complex digital systems
- Process automation scripting
- Protocol knowledge: PCIe, USB3/4, DP