Sr Principal Product Engineer

About the role

Cadence seeks a Sr Principal Product Engineer to lead the Perspec team, Cadence’s Portable Stimulus solution for SoC and system-level verification. The role drives deployment of PSS in large SoC environments, debugging complex generation and solver challenges, and shaping scalable verification methodologies. Working closely with semiconductor customers and Cadence R&D, the engineer will influence tool evolution, develop reference models, and support advanced use cases across simulation, emulation, and post‑silicon. The position requires deep expertise in SystemVerilog, UVM, embedded programming, and constrained‑random verification, with 12+ years of experience in SoC verification. The role offers a collaborative, innovative environment focused on technical excellence and customer impact.

What you’ll do

• Deploy Portable Stimulus in SoC programs
• Debug generation and solver issues
• Investigate modeling challenges
• Collaborate with R&D on tool issues
• Define scalable verification methodologies
• Develop reference models and best practices
• Support advanced system-level verification use cases
• Contribute to AI-assisted verification flows

What you’ll bring

• 12+ years SoC verification experience
• SystemVerilog & UVM expertise
• Embedded/bare-metal programming
• Constrained-random verification skills
• C/C++/Python scripting

Nice to have

• Portable Stimulus (PSS) exposure
• Perspec or other PSS tools
• PCIe/DDR/networking/ARM SoC experience
• Emulation/virtual platforms/post-silicon validation
• Verification methodology/library development

Skills

Benefits

• Career development opportunities
• Learning and development programs
• Employee well-being focus
• Collaborative culture
• Recognition of achievements

Education

MS