DSP / NPU Design Verification Senior Lead Engineer

About the role

DSP team, Qualcomm Hardware Engineering, designs high‑performance DSP/NPU cores for mobile, AI, and automotive SoCs. The Senior Lead Engineer drives design verification, builds SystemVerilog/UVM testbenches, creates automation, and ensures coverage and power‑aware validation across IP, subsystem, and SoC levels. Based in Bangalore with on‑site work, the role offers collaboration with global architecture, implementation, and post‑silicon teams.

What you’ll do

• Develop and improve SystemVerilog/UVM testbench architecture
• Create verification environments, test plans, and coverage models
• Run simulations, debug IP/subsystem/SoC issues, and perform gate‑level verification
• Implement power‑aware RTL verification and automation scripts
• Collaborate with global DSP design, implementation, and post‑silicon teams

What you’ll bring

Bachelor's degree in Computer Science, Electrical/Electronics Engineering or related field

Nice to have

• 2+ years experience in processor/ASIC design verification
• Expertise in SystemVerilog/UVM testbench architecture
• Experience with simulation, formal verification, and power‑aware verification
• Proficiency in Perl, Python, and Shell scripting
• Familiarity with Synopsys/Mentor/Cadence simulators

Skills