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Senior Analog Layout Design Engineer
Bengaluru, Karnataka, India Full-time
What you’ll do
- Design and implement transistor‑level layouts for analog and mixed‑signal ICs
- Perform layout verification using DRC and LVS and resolve violations
- Collaborate with circuit designers to optimize performance and yield
- Optimize layouts for parasitic reduction, matching, and process variations
- Execute floorplanning and block‑level integration
- Support tape‑out activities and resolve physical verification issues
What you’ll bring
- 4-6 years analog or mixed‑signal layout experience
- Proficiency with Cadence Virtuoso
Nice to have
- Strong knowledge of DRC and LVS verification
- Experience with transistor‑level layout of amplifiers, regulators, PLLs, ADCs, DACs
- Understanding of device matching, common centroid, shielding, guard rings
- Familiarity with Calibre for physical verification
- Exposure to advanced process nodes such as FinFET
Skills
Analog layoutCadence VirtuosoDRC verificationLVS verificationDevice matchingParasitic extractionFinFET processesPhysical verification
Education
Bachelor's or Master's degree in Electronics, Electrical Engineering, Microelectronics, VLSI Design or related field