Senior Analog Layout Engineer

About the role

Analog Layout Team at NXP Semiconductors designs high‑performance mixed‑signal IP. The engineer creates and verifies analog layout for PLLs, oscillators, data converters, power management and IO blocks using Cadence Virtuoso, performs EM/IR analysis and ESD reviews, and collaborates with global SoC and ACC teams. Based in Noida and Bangalore, India, on‑site work required.

What you’ll do

• Collaborate with design teams to define layout scope for high‑speed IO and clocking IP
• Work with ACC teams in Eindhoven, Austin, France and Noida on layout projects
• Provide regular support to SoC teams and gather requirements
• Conduct ESD and layout reviews throughout the design cycle
• Perform EM/IR analysis and generate back‑end views such as LEF and Milkyway

What you’ll bring

• Bachelor's Degree in Electronic or Electrical Engineering
• 3-7 years analog mixed‑signal layout experience
• Proficiency with Cadence Virtuoso
• Experience with 5nm‑40nm technology nodes
• Knowledge of PLL, oscillator, data converter, LDO layouts
• EM/IR analysis and ESD review expertise
• Understanding of layout matching and common centroid techniques
• Familiarity with LEF, NDM and Milkyway generation

Skills

Education

Bachelor's