Senior Technical Staff Engineer

About the role

Microchip Technology invites a Senior Technical Staff Engineer – Design to lead architecture and RTL design for high‑performance silicon in its Data Center Solutions unit. The role focuses on complex ASICs for cloud, big‑data, and AI/ML workloads, driving design excellence, low‑power strategies, and automation. Responsibilities include defining micro‑architecture, executing end‑to‑end RTL, collaborating with verification, physical, DFT, and system teams, mentoring senior staff, and influencing roadmap decisions for PCIe, CXL, NVMe, and SAS interconnects. Candidates must bring 15+ years of ASIC/SoC digital design experience, a bachelor’s degree in Electronics or Electrical Engineering, and deep expertise in SystemVerilog, lint, CDC, formal verification, synthesis, static timing, physical design, low‑power flows, DFT, and scripting (Tcl, Perl, Awk). Proficiency with high‑speed protocols and Cadence ASIC environments is essential. The position is on‑site in Bangalore, India, with up to 25% travel. Microchip offers a collaborative culture, growth opportunities, and a focus on employee development.

What you’ll do

• Lead architecture and micro‑architecture definition for complex IPs
• Drive end‑to‑end RTL design execution and silicon bring‑up
• Serve as technical authority ensuring high PPA standards
• Resolve cross‑domain design and EDA tool challenges
• Collaborate with verification, physical, DFT, system, product teams
• Guide low‑power, high‑performance design strategies
• Influence protocol and platform roadmap decisions
• Mentor senior and staff engineers with architectural reviews
• Represent design organization in technical reviews with leadership
• Apply data‑driven approaches to improve design quality and time‑to‑market
• Define and enforce design methodologies, sign‑off criteria, best practices
• Champion AI/ML‑assisted automation and intelligent workflows

What you’ll bring

• 15+ years ASIC/SoC digital design experience
• Bachelor’s degree in Electronics or Electrical Engineering
• SystemVerilog RTL design and micro‑architecture development
• Delivered multiple complex tape‑outs for high‑performance silicon
• Expertise in lint, CDC, formal verification, synthesis, static timing
• Strong physical design interaction knowledge (timing, power, congestion)
• Low‑power design methodology and flow experience
• Mandatory DFT knowledge (scan, testability, sign‑off)
• Scripting skills in Tcl, Perl, Awk
• Hands‑on with PCIe, CXL, NVMe, SAS/SATA protocols
• Cadence‑based ASIC design environment experience

Skills

Education

Bachelor