Senior Engineer, Digital Design Engineering

About the role

Analog Devices’ Digital Design Engineering team builds next‑generation VLSI circuits that power intelligent edge devices. The Senior DFT Engineer designs and implements testability features—scan chains, LBIST, MBIST, and boundary‑scan—to ensure robust silicon quality. Based in Bangalore, the role requires onsite collaboration with design, verification, and physical teams, with occasional travel for testing and client visits.

What you’ll do

• Collaborate with design team to embed DFT features
• Design scan chains, compression, and BIST structures
• Perform DFT DRC checks in RTL/Netlist
• Generate ATPG test patterns for SA and TF models
• Validate DFT structures in RTL and Netlist
• Coordinate with verification team on DFT plans
• Work with physical design on synthesis/STA constraints
• Debug test failures and mentor junior engineers

What you’ll bring

• Bachelor’s/Master’s in Electrical/Electronic Engineering
• 4-10 years of DFT experience
• Proficiency with Cadence/Siemens DFT tools
• Scripting in Perl, Tcl, or Python
• Strong RTL and ASIC design fundamentals

Skills