Sr Principal Design Engineer

About the role

RTL Design Engineer for DDR Memory Controller IP development team. Design and support RTL of DDR Memory Controller solution. Support DDR4/LPDDR4 protocols. Work with existing RTL, add new features, ensure clean configurations for verification regressions, support customers, maintain design clean for LINT and CDC guidelines.

What you’ll do

• Design and support RTL of DDR Memory Controller solution
• Add new features to existing RTL
• Ensure clean configurations for verification regressions
• Support customers
• Maintain design compliance with LINT and CDC guidelines

What you’ll bring

• BE/B.Tech/ME/M.Tech Electrical/Electronics/VLSI with RTL design experience
• RTL Design using Verilog mandatory
• SystemVerilog and UVM environment experience required
• AXI3/4 experience desired
• DDR Memory controller protocol experience highly desirable
• IP development team experience advantage

Skills