About the role

Lead verification for advanced IP, architect UVM-based environments, debug complex IP designs, mentor junior engineers, drive methodology improvements, collaborate cross-functional teams.

What you’ll do

Develop UVM-based verification environments for IP-level verification.
Perform debugging of complex IP designs and resolve issues efficiently.
Review and enhance verification test plans for completeness and coverage.
Drive testbench development, simulation, and regression strategies.
Mentor and guide junior engineers in verification best practices.
Collaborate with cross-functional teams for seamless integration and delivery.

What you’ll bring

Bachelor’s or Master’s degree in Electrical Engineering or related field.
Minimum 10 years of experience in IP verification.
Strong proficiency in SystemVerilog and UVM methodology.
Expertise in debugging complex IP designs.
Hands-on experience in testbench development and test plan reviews.
Proven ability to mentor and lead verification teams.

Nice to have

Experience in SERDES verification.
Familiarity with UCIe protocol and chiplet integration.
Knowledge of high-speed interfaces and related verification challenges.

Skills

SystemVerilogUVMDebuggingTestbench DevelopmentTest Plan ReviewMentoringCross-functional Collaboration

Benefits

Competitive compensation and benefits.

Education

Bachelor's or Master's in Electrical Engineering or related field.