Design-for-Test (DFT) Engineer

About the role

This role supports a client in the Information Technology & Services sector, focusing on driving design-for-test strategies for complex ASIC/SoC designs. The engineer implements DFT architectures, develops ATPG flows, and collaborates with RTL and physical design teams to ensure high test coverage and silicon readiness. This is an on-site position based in Bengaluru or Hyderabad.

What you’ll do

• Define and implement DFT architectures for complex ASIC/SoC designs
• Develop and integrate Scan-based DFT structures across blocks and top-level designs
• Develop, run, and debug ATPG flows for stuck-at, transition, and other relevant fault models
• Analyze ATPG coverage, fault reports, pattern quality, and test compression results
• Debug ATPG failures and identify design, constraint, or test-logic issues
• Work with RTL and design teams to resolve DFT-related implementation and verification issues
• Perform DFT rule checks and ensure test structures meet project requirements
• Support scan insertion, scan-chain verification, chain balancing, and scan connectivity checks

What you’ll bring

• 5+ years of hands-on experience in DFT/ASIC design and test engineering
• Strong expertise in ATPG (Automatic Test Pattern Generation)
• Extensive experience with Scan architecture and Scan insertion
• Strong understanding of scan chains, scan compression, test modes, and test coverage
• Experience debugging ATPG patterns, coverage issues, and DFT rule violations
• Good understanding of ASIC/SoC design flows and DFT implementation methodologies
• Experience working with RTL, synthesis, verification, and physical design teams
• Strong scripting/automation skills using languages such as Tcl, Python, or Perl

Skills

Benefits

₹15,00,000 - ₹80,00,000 a year