About the role

Sr. Principle DFT Engineer at NXP Semiconductors in Pune leads DFT design for MCU team, architecting DFT structures, instruments insertion, and simulation. Works with SOC lead/IP designers, DV team, BE lead, and test engineers to deliver DFT implementations, verify coverage, and bring up test patterns on silicon. Provides guidance to junior DFT engineers. Requires BS/MS in Electrical/Computer Engineering with 12+ years DFT experience, expertise in Mentor/Synopsys test generation tools, DFT techniques (JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500, MBIST, LBIST, SSN), and experience with synthesis, STA, back-end flows, Tessent shell flow, lab/test floor bring-up, debug, and DFT AI mindset. Responsibilities include defining DFT structure, creating test vectors, collaborating with physical design for timing closure, signing off DFT requirements, and working with testing team to bring up test patterns on silicon.

What you’ll do

Define and implement DFT structure, design and methodologies that include scan/mbist/jtag and functional testing
Create test vectors or oversee their creation
Collaborate with physical design team to close timing in DFT mode
Sign-off DFT requirements are being met
work with testing team to bring-up test patterns on silicon

What you’ll bring

BS/MS degree in Electrical/Computer Engineering with 12+ years of DFT experience
Hands-on expertise with Mentor/Synopsys test generation tools for large complex designs
DFT lead experience for complex SOC TO and Production
Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, and MBIST, LBIST, SSN

Nice to have

Experience with synthesis, STA and back-end implementation flows
Familiar with Tessent shell flow for DFT instruments insertion include MBIST, IJTAG, SSN, BSCAN, OCC etc
Solid Lab and test floor bring-up and debug experience
Yield estimation and test optimization
DFT AI mindset

Skills

Mentor/Synopsys test generation toolsDFT techniques: JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, MBIST, LBIST, SSNTessent shell flow for DFT instruments insertionSTAsynthesisback-end implementation flowsLab and test floor bring-updebugDFT AI mindset

Education

Bachelor's/Master's degree in Electrical/Computer Engineering