Senior Digital IP Design Manager

About the role

Digital IP Design team at onsemi develops digital datapath and subsystem IP for next‑generation CMOS image sensors and the Treo platform. The Senior Digital IP Design Manager leads the design of high‑performance, low‑power pipelines, drives core platform IP development, ensures automotive quality standards, and partners with architecture, verification, analog, firmware and software groups. Manages and mentors a sub‑team of digital designers in Bangalore, India, on‑site, with a focus on AI‑assisted productivity improvements.

What you’ll do

• Lead design of digital datapath IP and modules for CMOS image sensors
• Drive development of core platform digital‑on‑top and subsystem IP for Treo platform
• Ensure IP meets automotive quality, safety and reliability requirements
• Partner with architecture, DV, analog, mixed‑signal, system, firmware and software teams
• Provide technical guidance on RTL quality, low‑power, clocking and DFT
• Lead and mentor digital IP designers, fostering collaboration and continuous improvement
• Champion AI/ML‑driven automation tools to reduce cycle time

What you’ll bring

• 12+ years digital IC design
• 3+ years people management or technical leadership
• Strong background digital IP or SoC development
• Experience with automotive IP or semiconductor products
• Hands‑on RTL design (SystemVerilog/Verilog)
• Low‑power design techniques
• IP reuse and configurability
• Strong communication and cross‑functional influence

Skills