Senior Silicon Digital Design Engineer, Core IP

About the role

Platforms and Devices team at Google develops custom silicon that powers Google’s direct‑to‑consumer products. The Senior Silicon Digital Design Engineer defines microarchitecture, writes RTL and drives synthesis, timing and power closure for Core IP and ASIC integration. Works with multi‑site teams on verification, FPGA bring‑up and low‑power design. Bengaluru, Karnataka, India, on‑site.

What you’ll do

• Define microarchitecture for Core IP hardware
• Develop RTL implementations meeting power, performance, area goals
• Perform RTL coding, simulation, debug and verification checks
• Participate in synthesis, timing and power closure
• Assist FPGA and silicon bring‑up
• Collaborate with multi‑disciplined, multi‑site teams

What you’ll bring

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent

Nice to have

• 8 years digital logic design experience
• Proficiency in Verilog or SystemVerilog
• Experience with logic synthesis and low‑power techniques
• ASIC design methodology including clock domain and reset checks
• Scripting in C/C++
• Knowledge of formal verification and FPGA emulation

Skills