Senior Engineer I, Physical Design

About the role

Microchip AES Design team in Bangalore builds advanced physical design flows for large SoCs. The Senior Engineer I will lead full-chip physical implementation, including floor‑planning, place‑and‑route, CTS, verification and IP integration, while mentoring junior staff. Bangalore, on‑site role with occasional travel (0‑25%).

What you’ll do

• Own complete physical design of large and complex blocks from 40nm to 3nm nodes
• Perform floor‑planning, place‑and‑route and clock‑tree synthesis using Innovus/ICC2
• Execute physical verification and IP integration tasks
• Apply metric‑driven techniques for first‑pass silicon success
• Guide junior team members throughout project execution
• Collaborate with global implementation teams to resolve issues
• Communicate status and progress to leads regularly
• Occasionally travel to support project needs

What you’ll bring

• B.E/B.Tech/M.Tech in Electronics
• 4+ years physical design experience
• Expertise in floor‑planning, CTS, place‑and‑route, extraction, IR/EM checks
• Proficiency with Innovus or ICC2 and related backend tools
• Strong scripting skills in Perl, TCL, Python
• Experience with analog IP, hard/soft macros
• Understanding of synthesis and DFT concepts
• Excellent communication skills

Skills