Verified today
System IP Design Engineer
About the role
Tenstorrent's AI platform team builds high‑performance RISC‑V/ARM SoCs. The System IP Design Engineer owns microarchitecture and RTL implementation of power‑management subsystems, interrupt controllers, AXI interconnects and cache controllers, collaborating with architecture, firmware, software, DV and PD teams. Hybrid role based in Bengaluru, Karnataka, India.
What you’ll do
- Define microarchitecture and develop RTL for power‑management subsystems
- Drive verification closure, performance debug, synthesis, timing and power optimization
- Perform LINT, CDC/RDC and power‑intent checks
- Use DV tools such as Verdi and NCSIM for analysis
- Collaborate cross‑functionally from concept to silicon bring‑up
What you’ll bring
- 3–6 years ASIC design experience
- Proficiency in Verilog/SystemVerilog
- Experience with power management (clocking, reset, DVFS)
- Familiarity with RISC‑V or ARM SoCs and AXI/AHB/APB/CHI protocols
- Knowledge of functional safety ISO 26262
Skills
Benefits
- Competitive compensation
- Benefits package