Engineer, Staff, Sr. Staff Engineer, CPU Verification (RAS)

About the role

CPU Verification Team at SiFive focuses on ensuring the highest quality of CPU IP for RISC-V based processors. The role develops and maintains SystemVerilog/UVM testbenches, creates constrained‑random tests, and drives coverage to validate architecture and RAS features. Works closely with RTL designers to debug and resolve issues, primarily based in Hyderabad with on‑site work.

What you’ll do

• Develop and enhance block‑level and subsystem testbenches using SystemVerilog/UVM
• Extract verification requirements from architecture specs and review test plans
• Write directed and constrained‑random tests to achieve high functional and code coverage
• Debug simulation failures and collaborate with RTL designers to resolve issues
• Maintain and optimize automated regression setups

What you’ll bring

• 1+ years experience in Electrical or Computer Engineering
• Bachelor's or Master's degree in EE/CE or related field
• Strong knowledge of SystemVerilog and UVM
• Understanding of advanced computer architecture (pipelines, caches)
• Experience with constrained‑random verification and coverage metrics
• Proficiency in scripting languages such as Python, Perl, Bash

Nice to have

• Familiarity with RAS architecture and verification techniques
• Experience with ECC testing, parity checking, data poisoning, fault injection
• Knowledge of RISC‑V ISA and custom extensions

Skills