Design For Test - Lead

About the role

Weekday AI client team focuses on delivering robust silicon solutions for complex SoCs. The Lead DFT Engineer defines and implements DFT architecture, drives end‑to‑end test optimization, and supports post‑silicon validation across hierarchical projects. Bengaluru, on-site, hybrid schedule with occasional off‑site work as needed.

What you’ll do

• Define and implement DFT architecture for complex SoC designs
• Plan, track, and execute end‑to‑end DFT implementation across hierarchical projects
• Verify Scan, ATPG, MBIST, Boundary Scan methodologies and generate production‑ready test patterns
• Provide DFT mode STA support and contribute to timing closure activities
• Mentor junior engineers and improve DFT workflows

What you’ll bring

• 7+ years DFT experience
• Hands‑on hierarchical SoC DFT implementation
• Experience with Scan, ATPG, MBIST, Boundary Scan
• Gate‑level DFT verification and pattern generation
• Proficiency with Tessent or Synopsys DFT Compiler
• Support DFT mode STA and timing closure
• Mentoring junior engineers
• Collaboration across product, RTL, STA, physical design teams