Lead I/O Design Engineer

About the role

NXP India is seeking a Lead I/O Design Engineer to develop and validate high-performance I/O circuits for advanced semiconductor SoCs. Day-to-day work includes transistor-level design and simulation of GPIO, LVDS, DDR, SerDes, ESD, level shifters, buffers, and termination circuits using advanced CMOS nodes, along with signal integrity analysis, layout reviews, and silicon bring-up. The role is based in Bangalore and is a full-time position.

What you’ll do

• Design and develop custom IO circuits including GPIO, LVDS, LVCMOS, SSTL, HSTL, DDR interfaces, and high-speed SerDes support circuits
• Perform transistor-level design and simulation using advanced CMOS technology nodes
• Develop and optimize ESD protection circuits, level shifters, input buffers, output drivers, and on-chip termination circuits
• Conduct pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability
• Perform signal integrity analysis including IBIS model generation, package-aware simulations, and crosstalk and reflection analysis
• Drive layout reviews and work closely with physical design teams to ensure design quality and performance targets
• Support silicon bring-up, characterization, debugging, and production ramp activities
• Collaborate with system, package, reliability, and product engineering teams

What you’ll bring

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field
• 5-8 years of experience in Analog/Mixed-Signal or IO Circuit Design
• Strong understanding of CMOS device physics, analog circuit design fundamentals, IO architectures and standards, and ESD design methodologies
• Hands-on experience in custom circuit design using Cadence Virtuoso
• Expertise in SPICE-based simulators such as Spectre, HSPICE, or FineSim
• Experience with advanced technology nodes (16nm/7nm/5nm preferred)
• Good knowledge of LVS, DRC, EMIR, and reliability checks
• Familiarity with process corners, Monte Carlo analysis, and yield optimization techniques

Nice to have

• Experience with DDR4/DDR5, LPDDR, USB, PCIe, MIPI, or Ethernet interfaces
• Knowledge of package modeling and SI/PI analysis tools
• Understanding of ESD standards such as HBM, CDM, and IEC
• Experience in silicon validation and lab characterization
• Scripting skills in Python, Perl, Tcl, or SKILL
• Familiarity with IBIS and IBIS-AMI model generation

Skills

Education

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field