Verified 3 days ago
Senior Staff Engineer, RTL ASIC Design
About the role
Senior Staff Engineer, RTL ASIC Design at Marvell India Pvt Ltd, Bangalore. The role leads subsystem architecture, standards adoption, and design execution for complex SoCs, collaborating with vendors like Synopsys and ARM, and mentoring junior engineers. Bangalore, India, On-site
What you’ll do
- Own roadmap and execution of subsystem architecture
- Define and drive KPIs (performance, power, security, scalability)
- Work with third‑party vendors on customization and IP roadmap
- Deliver subsystem collateral (specs, PRDs, guides, benchmarks)
- Review verification test plans and methodologies
- Collaborate with SoC Chief Engineers, Product Architecture, DFT, FW/SW, System teams
- Mentor junior team members
What you’ll bring
- 8+ years ASIC design
- Verilog/SystemVerilog RTL coding
- SystemVerilog assertions
- ASIC design flow
- Complex SoC experience
- Peripheral IPs (I3C,I2C,UART,USB)
- Vendor IP integration (Synopsys, Cadence, ARM)
- Scripting (Perl/Python/Shell)
Skills
Benefits
- Competitive compensation
- Inclusive work environment
- Growth and development opportunities