Senior Silicon Physical Design Engineer

About the role

The AI and Infrastructure team at Google Cloud develops custom silicon solutions powering direct-to-consumer products. As a Senior Silicon Physical Design Engineer in Bengaluru, you drive physical design methodologies, manage timing and power for SoC partitions, and collaborate with DFT and architecture teams. This on-site role requires 8+ years of experience in advanced ASIC design.

What you’ll do

• Define and drive the implementation of physical design methodologies.
• Take ownership of one or more physical design partitions or top level.
• Manage timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design related rule sets for the functional design engineers.

What you’ll bring

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience with advanced design, including clock/voltage domain crossing, design for testing (DFT), and low power designs.
• Experience with system on a chip (SoC) cycles.
• Experience in high-performance, high-frequency, and low-power designs.

Nice to have

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in coding with System Verilog and scripting with TCL.
• Experience with layout verification and design rules.
• Experience with very large scale integration (VLSI) design in SoC or multiple-cycles of SoC in ASIC design.

Skills

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.