Sr. Principal Design Verification Engineer

About the role

Marvell Data Centre Engineering (DCE) – Compute & Storage (CCS) BU builds high‑performance ASIC platforms for cloud, enterprise and automotive. The Sr. Principal Design Verification Engineer leads end‑to‑end PCIe/CXL subsystem DV, architecting UVM testbenches, driving test plan creation, and coordinating cross‑functional teams for post‑silicon validation. Based in Bangalore, the role is on‑site with full‑time commitment.

What you’ll do

• Define and drive DV process improvements
• Collaborate with IP, Subsystem, and SoC teams on test plan creation
• Architect and implement UVM testbenches
• Execute test plans for design correctness and performance
• Debug simulation failures and resolve root causes
• Coordinate with Architecture, Chip Lead, Emulation, and Program Management
• Support post‑silicon validation and bring‑up activities
• Lead cross‑functional DV execution

What you’ll bring

• Master’s or Bachelor’s degree
• 18+ years of design verification experience
• Lead end‑to‑end PCIe/CXL subsystem DV
• UVM and C coding
• ARM architecture and AMBA bus knowledge
• PCIe/CXL interface expertise
• Cadence/Synopsys/Mentor/ARM verification tools
• Scripting in Tcl/Perl

Skills