Senior Gate-Level Simulation Verification Engineer

About the role

SoC Design Verification / Silicon Sign-off team ensures final netlist correctness before silicon tape-out. The Senior Gate-Level Simulation Verification Engineer leads GLS strategy, builds and debugs UVM/SystemVerilog testbenches, scripts automation, and validates timing, power and DFT logic. Bengaluru, Karnataka, India, on-site.

What you’ll do

• Own and execute GLS verification strategy for IPs and full-chip SoCs
• Maintain and debug UVM/SystemVerilog testbenches in zero-delay and back-annotated simulations
• Develop automation scripts in Perl, Python, and Shell for regressions and reporting
• Validate design-for-test logic including scan-chain, BIST, and JTAG at gate level
• Perform power-aware GLS using UPF to check isolation cells and power-gating
• Collaborate with RTL, Physical Design, and DFT teams to triage and resolve failures

What you’ll bring

• 8+ years ASIC verification with gate-level simulation
• Experience with Synopsys VCS, Cadence Xcelium or Siemens Questa
• Strong debugging using Verdi or DVE
• Proficiency in Perl or Python scripting
• Understanding of RTL vs GLS environments
• Bachelor's or Master's in Electrical/Computer Engineering
• Experience with UVM/SystemVerilog testbenches
• Power-aware GLS using UPF

Skills