Senior Lead ASIC Design Engineer - Digital Design

About the role

Define hardware architectures for AI inference SOCs. Contribute micro-architecture definition, evaluate trade-offs for complex SOCs. Own features end-to-end: spec → RTL → integration → synthesis → debug. Collaborate with physical design teams on synthesis, timing, power. Collaborate with verification team to ensure design correctness. Model workloads, analyze bottlenecks, validate AI inference use cases.

What you’ll do

• Define hardware architectures for AI inference SOCs
• Contribute micro-architecture definition, evaluate trade-offs for complex SOCs
• Own features end-to-end: spec → RTL → integration → synthesis → debug
• Collaborate with physical design teams on synthesis, timing, power
• Collaborate with verification team to ensure design correctness
• Model workloads, analyze bottlenecks, validate AI inference use cases

What you’ll bring

• 7+ years of experience in ASIC/SoC RTL design
• Strong Verilog/SystemVerilog coding skills
• Solid understanding of synthesis, timing, and power analysis
• Experience with Lint/CDC/RDC flows
• Strong debugging and root-cause analysis capability

Skills