RTL(IP) Design Engineer/Infra - Sr Lead/Staff

About the role

Hardware Engineering team at Qualcomm focuses on NoC and interconnect infrastructure for next‑gen SoCs. The Senior Lead designs, specifies, and implements interconnect IP, collaborates with SoC, verification, physical design and performance teams, and drives micro‑architecture of debug hooks. Bangalore office, on‑site, leading cross‑functional teams to meet performance and silicon validation goals.

What you’ll do

• Define specifications and architecture for NoC IP
• Develop and verify RTL implementations
• Coordinate with SoC performance and silicon validation teams
• Manage front‑end design tasks and project milestones
• Lead cross‑functional teams to resolve complex hardware issues

What you’ll bring

• 8+ years IP/SoC design and micro‑architecture experience
• Strong knowledge of interconnect protocols (CHI, AHB, AXI, ACE)
• Proficient in Verilog RTL coding and digital design
• Experience with multi‑core ARMv8/v9 architecture and coherency
• Hands‑on with Synopsys DC synthesis, DFT, formal verification
• Familiar with Lint, CDC, PLDRC, CLP tools
• Effective communication and leadership skills

Skills