Senior Engineer Level 1

About the role

Engineering Services team at Arrow Electronics focuses on design-for-test (DFT) solutions for semiconductor products. The Senior Engineer Level 1 develops and validates scan insertion, MBIST, JTAG, ATPG, and pattern validation across block and full-chip levels, and leads comprehensive DFT planning with cross‑functional teams. Bangalore, India, on-site role.

What you’ll do

• Design and insert scan and MBIST structures into ASIC designs
• Create and validate ATPG and pattern tests at block and full‑chip levels
• Develop comprehensive DFT strategies and coordinate with cross‑functional teams

Nice to have

• Hands‑on experience with scan insertion, MBIST, JTAG, ATPG, and pattern validation
• Ability to develop and validate DFT plans and drive implementation
• Experience with timing analysis and sign‑off for DFT modes

Skills