Sr. Principal Engineer

About the role

Experienced STA Leader to drive end‑to‑end timing closure and signoff for SOC. Own timing signoff criteria, clocking, constraints, and validation. Interface with IP, Functional Integration, DFT, Verification, and Physical implementation teams. Manage functional/scan/MBIST timing constraints across multiple clocks, develop SOC IO constraints, and handle bottom‑up partition‑level integration. Perform advanced timing analysis, debug, ECO creation with signal integrity & EM/IR, and build SDF, GLS, and timing/noise models. Work on 28nm, 16nm, 10nm, 7nm nodes using EDA tools (RC, DC, PT, PTSI). Contribute to flow/methodology scripting and support design implementation.

What you’ll do

• Manage functional/scan/MBIST timing constraints across multiple clocks.
• Develop SOC IO constraints and drive timing signoff criteria.
• Own bottom-up partition-level integration and top-down design partition constraints.
• Perform advanced timing analysis, debug, and timing convergence.
• Create ECOs with signal integrity & EM/IR considerations.
• Debug timing failures using SDF, GLS.
• Work on 28nm, 16nm, 10nm, 7nm nodes.
• Use EDA tools RC, DC, PT, PTSI.
• Contribute to flow/methodology scripting for design implementation.

Skills