Design-for-Test Engineer

About the role

This Design-for-Test Engineer role supports a client in the Information Technology & Services industry, driving DFT strategy and implementation for complex ASIC/SoC designs. Day-to-day work includes defining DFT architectures, developing and debugging ATPG and Scan flows, analyzing fault coverage and pattern quality, and collaborating with RTL, Physical Design, Verification, and Product Engineering teams to deliver production-ready test solutions. The position is based in Hyderabad or Bengaluru and is on-site.

What you’ll do

• Define and implement DFT architectures for complex ASIC/SoC designs
• Develop and integrate Scan-based DFT structures across blocks and top-level designs
• Develop, run, and debug ATPG flows for stuck-at, transition, and other relevant fault models
• Analyze ATPG coverage, fault reports, pattern quality, and test compression results
• Debug ATPG failures and identify design, constraint, or test-logic issues
• Perform DFT rule checks and ensure test structures meet project requirements
• Support scan insertion, scan-chain verification, chain balancing, and scan connectivity checks
• Collaborate with physical design teams to ensure DFT structures are physically implementable and timing-aware

What you’ll bring

• 5–20 years of hands-on experience in DFT/ASIC design and test engineering
• Strong expertise in ATPG (Automatic Test Pattern Generation)
• Extensive experience with Scan architecture and Scan insertion
• Strong understanding of scan chains, scan compression, test modes, and test coverage
• Experience debugging ATPG patterns, coverage issues, and DFT rule violations
• Good understanding of ASIC/SoC design flows and DFT implementation methodologies
• Experience working with RTL, synthesis, verification, and physical design teams
• Strong scripting/automation skills using Tcl, Python, or Perl

Skills