Principal Senior Principal STA Full Chip Expert

About the role

Custom Processor/ASIC team at Marvell builds high‑performance processor SOCs for server, 5G/6G and networking applications. The Principal STA Full Chip Expert leads the global timing flow, develops IP constraints, mentors cross‑disciplinary design teams and automates workflows with TCL/Perl scripts. Bangalore office, on‑site work model.

What you’ll do

• Run, support and maintain the global timing flow for multi‑GHz SOC designs
• Develop and integrate timing constraints and manage ECO flows
• Collaborate with Digital, RTL, Analog and DFT teams to ensure block timing closure
• Provide technical direction, coaching and mentoring to team members
• Write automation scripts in TCL and Perl to improve productivity

What you’ll bring

• BSEE or MS degree
• 12-25 years timing analysis experience
• PrimeTime or equivalent EDA tool expertise
• Tape‑out experience for high‑performance SOCs
• Proficiency in timing concepts: setup, hold, clocking, corners, noise, variation
• Perl and TCL scripting skills
• Strong communication and mentorship abilities

Skills

Education

BSEE or MS