Senior Network Processor IP Verification Lead Engineer

About the role

Qualcomm Hardware Engineering team drives next‑generation network processor designs. The Senior Network Processor IP Verification Lead Engineer develops verification strategies, builds UVM testbenches, and leads coverage closure for complex ASICs, collaborating with multi‑site teams in the US and India. Role is based in Bangalore with on‑site work model, leading junior engineers and coordinating cross‑functional verification efforts.

What you’ll do

• Develop verification strategy and UVM testbench architecture
• Lead junior engineers and manage verification project plans
• Perform coverage analysis, bug triage, and sign‑off for IP blocks
• Collaborate with design, SOC, SW, and validation teams
• Conduct post‑silicon debug and IP integration testing

What you’ll bring

• 5-8 years digital front‑end ASIC verification experience
• Proficiency in RTL verification using SystemVerilog/UVM
• Scripting in Perl or Python for automation
• Experience with low‑power verification and clock domain crossing
• Knowledge of bus protocols such as AHB and AXI
• Familiarity with formal verification tools

Skills

Education

Bachelors or Masters in Electrical/Electronics Engineering or related field