Principal Digital Verification Engineer

About the role

Microchip Technology invites a Principal Digital Verification Engineer to lead advanced verification of digital products. The role focuses on designing and executing UVM-based verification frameworks, creating test plans, and ensuring silicon validation. Responsibilities include owning the verification lifecycle, developing methodologies, coding SystemVerilog and SVA, running regressions, analyzing results, and collaborating with design teams to debug failures. The position requires deep expertise in UVM, SystemVerilog, and coverage models, along with strong problem‑solving, communication, and self‑motivation. Preferred experience includes scripting (Python, Perl, Tcl), memory product knowledge, and mixed‑signal simulation. Candidates must hold a bachelor’s degree in Electrical Engineering and have at least ten years of UVM verification experience. The role is based in Bangalore, India, and involves up to 25 % travel. Microchip offers a collaborative culture, growth opportunities, and a supportive environment for innovation.

What you’ll do

• Own verification flow from test plan to silicon validation
• Develop and improve verification methodology
• Define architecture and implement UVM frameworks
• Write UVM code, tests, sequences, RAL, coverage, SVA
• Run regressions, analyze results, debug failures
• Support post‑silicon debugging

What you’ll bring

• Expertise in UVM methodology
• Extensive experience building UVM-based verification frameworks
• Proficiency in System Verilog coding
• Ability to write System Verilog Assertions (SVA)
• Excellent problem‑solving skills
• Strong communication and teamwork
• Self‑motivated and quality‑focused
• 10+ years UVM verification experience
• Bachelor’s degree in Electrical Engineering

Nice to have

• Scripting knowledge (Python, Perl, Tcl)
• Experience with memory products
• Experience in mixed‑signal simulation environments

Skills

Education

Bachelor