Senior Lead Design Verification Engineer, System Memory Management Unit

About the role

Qualcomm Hardware Engineering team designs and verifies cutting‑edge System Memory Management Units for next‑gen SoCs. The Senior Lead Design Verification Engineer owns the SMMU IP testbench, creates verification environments, and collaborates with architects and SW teams to debug silicon and close functional coverage. Bangalore, India, on‑site, Full‑time role focusing on high‑performance verification and performance modeling.

What you’ll do

• Own and maintain the SMMU verification testbench and collateral
• Develop test plans and cases to achieve functional coverage goals
• Collaborate with system architects, design, and emulation teams to debug failures
• Create and maintain verification scripts and tools
• Analyze post‑silicon issues with design and software teams
• Support SoC performance modeling and latency analysis

What you’ll bring

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering or related field with 3+ years hardware verification experience
• Master's degree in related field with 2+ years experience
• PhD in related field with 1+ year experience

Nice to have

• UVM and SystemVerilog verification expertise
• Strong debugging and analytical skills
• Knowledge of ARM bus protocols (AXI, AHB, APB, CHI)
• Experience with verification tools such as Certitude, VC Formal, Fishtail
• Performance modeling for latency and bandwidth analysis
• Developing monitors, scoreboards, and sequencers

Skills

Education

Bachelor's