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Senior Engineer (Level 1)- DFT
About the role
Senior Engineer (Level 1)- DFT responsible for end-to-end DFT activities including Scan insertion, BIST, MBIST, ATPG, IP tests, and Pattern Validation. Leads DFT plan development, drives implementation, performs timing analysis, and signs off. Collaborates with cross-functional teams and manages JTAG integration, validating patterns at block and full-chip levels.
What you’ll do
- Lead Scan insertion, BIST, MBIST, ATPG, IP tests, Pattern Validation.
- Drive DFT plan development and implementation.
- Perform DFT mode timing analysis and sign off.
- Collaborate with DFT and cross-functional teams.
- Validate patterns at block and full-chip levels.
- Manage JTAG integration.