About the role

Qualcomm seeks a Lead/Staff/Sr Staff CPU Integration/Physical Verification CAD Engineer to enable floor-planning, physical design, and sign-off for its Oryon CPU cores. The role involves developing high-performance chip solutions using Python, Tcl, and industry-standard tools like Cadence Innovus and Siemens Calibre. This position is based in Bangalore, India, or Noida, Uttar Pradesh, India.

What you’ll do

Enable floor-planning, physical design, and physical design verification for Oryon CPU cores
Perform analysis and timing sign-off for high-performance chips
Develop and manage place-and-route flows
Utilize Python and Tcl for automation and tool scripting
Collaborate with cross-functional teams to meet performance requirements
Apply knowledge of data structures and algorithms to solve engineering challenges

What you’ll bring

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field
6+ years of Hardware Engineering or related work experience
Hands-on experience in development of high-performance chips
High level of programming proficiency in Python and Tcl
Knowledge of data structures and algorithms

Nice to have

Experience with automation in physical design flows
Broad experience with Physical Design tasks including place-and-route and timing sign-off
Experience with advanced technology nodes (5nm or lower)
Strong user of industry-standard PDV tools such as Siemens/Mentor Calibre
Strong user of industry-standard place-and-route tools such as Cadence Innovus
Proven track record of managing and regressing place-and-route flows

Skills

PythonTclPhysical DesignPlace-and-RouteTiming Sign-offData StructuresAlgorithmsAutomation

Education

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field