Senior Engineer - Memory Circuit Design Verification

About the role

Micron Technology seeks a Senior Engineer for Memory Circuit Design Verification in Hyderabad. The role focuses on fastspice-based verification of DRAM critical timings, full-chip analog spice simulation, test case development, and collaboration with cross‑geo teams. Requires 3+ years experience, Master’s preferred, expertise in Fastspice, Virtuoso, FineSim, Hspice, Xcelium, SimVision, WaveView, UVM, SV, scripting in Perl/Python, and knowledge of CMOS/FinFET, static timing analysis, and DRAM memory concepts.

What you’ll do

• Minimum 3 yrs of experience with Masters background is preferrable.
• Responsibilities for fastspice (Primesim/FineSim/SpectreFx) based verification to sign-off DRAM Critical Timings.
• Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes.
• Full Chip Analog Spice Simulation and Analysis across PVTs and Speed Grades.
• Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs.
• Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features.
• Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.
• collaborate with cross—geo teams (US, Japan) to develop new verification flows to take on the challenges in DRAM and emerging memory design.
• Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.

What you’ll bring

Minimum 3 yrs of experience with Masters background is preferrable.

Nice to have

• Good understanding of analog/mixed signal circuits and full-chip activities
• Fundamental knowledge of CMOS and FinFET technologies.
• Experience in Analog and Mixed signal Verification, understand the usage of tools like Virtuoso, FineSim, Hspice, Xcelium, SimVision, WaveView.
• Hands on experience in building SPICE testbenches at Block, Full chip Level. Hand on experience in building the Analog Full Chip Verification environment is a plus.
• Good Knowledge on Static Timing Analysis Concepts
• Hands on experience in SV, UVM based Verification
• Good scripting skills using Perl, Python is a plus.
• Previous work experience in Memory (HBM/DRAM/SRAM) related fields is a plus.
• Good Knowledge on DRAM Memory and Critical Timing Concepts is a big plus.
• Must possess good communication, debugging skills and ability to work well in a team.

Skills

Education

Master's