Senior Physical Design Engineer

About the role

Semiconductor Design Team at Microsoft builds cutting-edge ASICs for next‑generation products. The Senior Physical Design Engineer leads block‑to‑chip level physical implementation, including floorplanning, synthesis, placement, CTS, routing, timing closure and sign‑off verification. Works on‑site in Bengaluru, Karnataka, India and Hyderabad, Telangana, India, with occasional travel.

What you’ll do

• Implement physical design flow for blocks, subsystems, sub‑chips and full chips
• Develop and automate design scripts and methodologies
• Perform timing closure, power optimization and IR‑drop analysis
• Coordinate with technology, IP and vendor teams for selections
• Provide status updates, risk assessments and issue mitigation to management

What you’ll bring

• 8+ years experience in physical design
• Bachelor's or Master's in Electrical or Computer Engineering
• Experience with tapeout of complex ASICs
• Proficiency in floorplanning, synthesis, placement, CTS, routing, static timing analysis
• Experience with physical verification and power analysis

Skills