Senior Memory Mask Design Engineer

About the role

Senior Memory Mask Design Engineer at NVIDIA’s Memory Design team – responsible for implementing IC layout of high‑performance CMOS memory circuits in 3nm‑7nm nodes, leading architecture and layout of key memory subsystems, and driving physical verification and optimization. Works on compiler‑driven design flows, IR/EM mitigation, and advanced layout challenges while mentoring junior engineers. Bengaluru, India, Hybrid work model with on‑site presence.

What you’ll do

• Implement IC layout of high‑speed CMOS memory circuits
• Lead architecture and layout of memory subsystems
• Direct custom layout and verification of memory cells
• Optimize physical verification activities
• Drive resolution of compiler‑generated layout issues
• Guide IR drop and EM mitigation strategies
• Develop memory compilers and drive optimization
• Mentor junior engineers

What you’ll bring

• 6+ years memory layout experience
• B.E./M.Tech in Electronics
• Expertise in advanced CMOS process nodes
• Proficiency with Cadence EDA tools
• High‑performance memory layout
• Floor planning and macro assembly
• Physical verification (DRC, LVS, EM/IR)

Skills